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SPI NOR flash is running out of gas, at least for automotive applications, so Infineon Technologies is pairing the proven Low-Power Double Data Rate (LPDDR) interface with NOR flash.
The semiconductor manufacturer claims to be the first in the industry to combine LPDDR with a non-volatile memory other than DRAM, making it a new category of product, Sandeep Krishnegowda, VP of marketing and applications for flash solutions at Infineon, told EE Times in a briefing. The combination is being driven by the transformation of automotive architectures toward zone and domain controllers within software-defined vehicles. “There’s a lot of real-time code execution that needs to happen that is safety-critical,” he said.
The increasing real-time demands of modern automotive architectures have demonstrated that Octo SPI devices with an eight-pin interface can’t keep pace, Krishnegowda added. “When we think about executing code, it’s not just about the raw bandwidth that you can get; it’s also about having extremely fast random accesses to the memory. NOR flash as a technology offers that.”
Now available for sampling, Infineon’s Semper X1 LPDDR flash delivers 3.2-GB/s bandwidth, which is 8× higher than Octal xSPI NOR at 400 MB, while random access is 20× faster.
“This is what’s going to enable software-defined vehicles,” Krishnegowda said. These vehicles have a whole host of sensors all over the car feeding into zone controllers that are making safety-critical decisions in real time, rather than everything being sent to a central domain electronic control unit (ECU), he said. “The architecture choices are becoming more complex.”
That complexity is driving cost, even as the number of ECUs is being consolidated—there are hundreds of them, , said during the briefing. “That’s just too many to manage.” The consolidation of functions is happening in conjunction with the proliferation of real-time processing, he added.
But rather than trying to create a new interface to solve the problem, or use an emerging memory, Infineon decided the best route was to take a proven process technology for flash and combine it with a proven interface, Krishnegowda said, both of which already have track records of meeting the stringent functional safety requirements of automotive. He noted that Infineon has tweaked the LPDDR interface somewhat to improve performance while taking advantage of its ability to scale to 2.1 GHz, as well as expand from an eight-lane bus to 16.
Wong said that by taking two proven technologies and combining them, Infineon is reducing risk. Despite minor tweaks to make them compatible and improve performance, the company is not looking to create a proprietary memory technology, he added.
“We are working with the industry to drive standardization of this LPDDR for non-volatile memories,” Wong said. “It’s not a one-shot deal where Infineon has a proprietary solution. We absolutely see a broader story.”
While there’s been lots of discussion about how emerging memories, such as magnetoresistive random-access memory (MRAM), resistive RAM (ReRAM) and phase-change memory (PCM), might meet automotive demands, the industry highly values reliability and longevity. NOR flash has been a workhorse memory for automotive applications, steadily gaining traction thanks to the growing amount of telematics, as well as all of the infotainment features and functions in the center console that require instant-on capabilities.
Volatile, low-power DRAM, however, is expected to play an ongoing role in supporting autonomous capabilities with companies like Micron Technology, which is proactively readying its LPDDR5 for Level 5 autonomy.
NOR flash has been winning on the automotive front, and Infineon’s new part is coming to market at a good time, Jim Handy, principal analyst with Objective Analysis, told EE Times in an exclusive interview.
“Automotive processors are getting increasingly complex with the move toward autonomous vehicles,” he said. “They need the most advanced CMOS logic processes, but those processes don’t support embedded NOR, so they have to either use an external NOR chip or an embedded emerging memory technology like MRAM, ReRAM or PCM.”
However, external NOR typically communicates with the processor chip via SPI, which is slow, Handy added—especially in comparison with embedded NOR. The increasing complexity of the processors is demanding more and more bandwidth.
“This presents a conflict,” he said. The processor’s bandwidth requirements are on the rise while the available bandwidth just dropped down a big step by going to external SPI NOR. “Putting NOR on the LPDDR bus helps out a lot. It’s much faster than SPI, and it can support the very large off-chip memories that these increasingly complex processors need.”
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