[ad_1]
//php echo do_shortcode(‘[responsivevoice_button voice=”US English Male” buttontext=”Listen to Post”]’) ?>
“Shift left for Architects…”
“What is shift left security?…”
“Adopting a shift left culture…”
Search the term “shift left” and you’ll see dozens of articles discussing the definition of shift left, how shift left can improve operations and results in a variety of industries, or even why shift left doesn’t work. Clearly it’s a topic of much discussion, and many companies are actively working towards implementing shift left principles and practices…or so they think. But a successful shift left strategy contains many components—ignoring even one of them reduces the chance of achieving the gains you’re expecting to see.
Larry Smith, a software engineer, is credited with coining the phrase “shift left” back in 2001, in an article focusing on improving the flow between software development and quality assurance testing1. He asserted that, to improve the overall software development process, teams needed to develop test cases earlier, perform testing earlier, and automate testing as much as possible. His conclusion, “Bugs are cheap when caught young,” encapsulates the concept and value of the shift left approach.
In the semiconductor industry, integrated circuit (IC) design and implementation is a complex process involving multiple stages. Getting designs to manufacturing on schedule, creating robust, reliable designs that stand the test of time, and releasing products that perform as intended all depend on achieving and maintaining high productivity and quality of results throughout the design flow. Companies continuously look for opportunities to improve their outcomes and achieve their business objectives. Shift left holds the promise of delivering both improved productivity and product quality by implementing targeted physical verification activities during the design and implementation stages. But shifting your IC design flow left is not simply the transference of verification to earlier stages of the design flow. To fully realize the potential benefits, an effective shift left implementation accounts for multiple elements that will impact the organization and its chances of success. It is a holistic approach to IC design and verification that seeks to optimize the entire flow and the results obtained. And it starts with understanding just how a shift left implementation changes your design flow methodology.
In a traditional IC design flow, “signoff,” or final physical verification (PV) of the layout, is performed on the completed layout at the end of the design cycle, using rule decks the foundry has qualified for the target process node. Signoff physical verification (PV) processes are comprehensive, including design rule checking (DRC), layout vs. schematic (LVS) verification, and electrical rule checking (ERC), as well as design for manufacturing (DFM) optimizations that are needed to prepare a design for manufacturing. A design must pass signoff verification before the foundry will accept it for manufacturing. As such, any errors found during signoff must be corrected before the tapeout can occur.
All too often, when each of the components of a system-on-chip (SoC) design have been completed and compiled into a single chip, signoff verification produces a flurry of unexpected results. Correcting these errors can be extremely difficult in layouts that now have very little flexibility or space. Making one correction often generates more errors, which must then also be corrected, generating round after round of difficult debugging and time-consuming verification iterations that delay the final tapeout date.
The shift left philosophy seeks to reduce or eliminate these iterations by shifting some physical verification analysis into earlier stages of the design flow, where errors in each component can be corrected more quickly and easily, without creating significant impacts on the layout later. However, note the use of the word “some.” Simply using signoff verification tools on early layouts is not the answer. When design layouts are “dirty” or incomplete, as they are in early stages, signoff verification runtimes will not only be extremely time-consuming, but they will also return thousands, if not millions, of errors. While many of these errors turn out to be caused solely by the incomplete nature of the layout, designers must still spend huge amounts of their time debugging these error results to reach that conclusion. Hardly the increase in productivity you were hoping for.
You might say, but our company already has verification functionality built into our design or P&R tool! Custom design and P&R tools are designed and intended for a specific process—design creation and implementation—and they perform that function well. Forcing custom and P&R tools to perform verification processes for which they are poorly suited from a quality of results or performance perspective guarantees design issues will remain undetected until signoff, requiring time-consuming iterations back through design or P&R.
Design-stage physical verification should make use of tools and verification capabilities intentionally designed to provide appropriate verification for that stage of the IC design cycle, while benefitting from comprehensive, full-featured design-stage verification and optimization functionality proven across hundreds of design companies and all leading foundries. Rather than the comprehensive coverage provided by signoff verification, shift left verification should make use of targeted and selective check selection that enables designers and engineers to focus on finding and correcting key systemic or critical errors that will create untenable layouts if left to propagate through the design as it progresses. Enabling designers and engineers to pinpoint “hotspot” layout locations that generate the majority of these types of layout errors helps designers and engineers find and clear them more quickly. Innovative verification functionality, such as early short isolation, symmetry verification, gray-boxing of missing or incomplete components, and automated waiving of known errors, not only reduces verification runtimes, but eliminates unnecessary time spent debugging errors that are irrelevant to design-stage verification.
Machine learning (ML) and other artificial intelligence (AI) techniques can help automate and refine design-stage layout analysis by identifying configurations of results across separate checks that can act as signals to help designers identify the optimal correction techniques. Using the DRC and LVS verification tools preferred by foundries and design companies alike ensures corrections will be compliant with signoff requirements, while automated back-annotation ensures changes are integrated into the design database for later design flow stages. Tight interfaces between design-stage verification tools and custom design and P&R tools provide design companies with the flexibility to create a mix of best-in-class tools and processes that maximize both productivity and quality of results across the design flow.
However, when introducing new tools into an established flow, one critical consideration is the impact it imposes on the people who execute the various stages of the IC design cycle. Depending on the type of designs your company produces and the size of your company, you may have multiple teams of specialized engineers who pass designs from one stage to another, or you may have small teams that perform multiple stages. Before beginning a shift left implementation, companies should consider the current organization, and how to introduce changes to established methodologies and workflows. Resistance to change may be real, but so are the productivity benefits of a shift left implementation.
For example, designers and place-and-route (P&R) engineers who were not previously responsible for verification run configuration might feel overwhelmed by the thought of the plethora of options and decisions. Introducing them to automated, user-friendly, intelligent tools and interfaces that simplify, speed up, and optimize job configuration and invocation enables them to take on these new responsibilities more easily and efficiently.
Likewise, enabling both custom IC designers and P&R engineers to run full-featured design-stage physical verification from their favorite custom design or P&R cockpit, and immediately view/debug results in that same familiar environment, with access to the same rule decks and engines used in signoff verification, enhances their productivity while improving quality of results. When change brings real improvements in personal and team productivity, such as a significant reduction in the number of time-consuming verification iterations required, or the ability to correct and verify a custom layout issue almost instantaneously, individuals who are being asked to change their workflow can directly see the value a shift left strategy brings to themselves, as well as the organization.
Enhanced design-stage verification also makes use of innovative functionality to implement types of verification that were previously non-existent in industry design enablement flows. For example, enhanced automated waiver processing and results database classification allow designers to waive errors they can’t do anything about or don’t need fixing, while gray-box functionality helps isolate incomplete components from verification to avoid creating unnecessary errors. Once verification is run, minimizing, grouping, and visualizing error results helps designers and engineers identify systemic and critical design issues and their root causes more quickly, efficiently, and accurately. Automated correct-by-construction layout modifications and optimizations that enhance both manufacturing robustness and design quality enables design companies to avoid tying up expensive P&R licenses to perform design for manufacturing (DFM) optimizations before verification.
In short, a well-planned shift left strategy doesn’t just throw signoff verification tools and techniques into design and implementation stages in the hopes that will help with early design verification. Implementing the right tools and techniques to help designers and P&R engineers eliminate critical and systemic errors earlier and faster in the design flow can minimize the number of complex, time-consuming signoff verification iterations required, enabling design teams to meet tight tapeout schedules while still ensuring optimal design efficiency, performance, reliability, and yield. Shifting left can not only free up critical time and resources in delivery schedules, but also ensure design companies can maintain or improve product quality in the face of increased design complexity, expanding design functionality, and tightening market schedules.
More information
For additional information on how your company can benefit from a shift left with the Calibre nmPlatform, our shift left technical paper series provides you with both strategic and implementation guidance.
Shift left with Calibre to optimize IC design flow productivity, design quality, and time to market
The four foundational pillars of Calibre shift left solutions for IC design & implementation flows
What does shift left with Calibre mean for IC designers?
Authors
Michael White is the senior director of physical verification product management for Calibre Design Solutions at Siemens EDA, a part of Siemens Digital Industries Software. Prior to Siemens, he held various product marketing, strategic marketing, and program management roles for Applied Materials, Etec Systems, and the Lockheed Skunk Works. Michael received a B.S. in System Engineering from Harvey Mudd College, and an M.S. in Engineering Management from the University of Southern California.
David Abercrombie is the marketing director for Calibre multi-patterning, machine-learning, and licensing applications at Siemens EDA, a part of Siemens Digital Industries Software. David drives the roadmap for developing new and enhanced EDA tools to solve the growing challenges in advanced physical verification and design for manufacturing (DFM). Prior to joining Siemens, David managed yield enhancement programs in semiconductor manufacturing at multiple companies. He is extensively published in papers and patents on semiconductor processing, yield enhancement, and physical verification. David received his BSEE from Clemson University, and his MSEE from North Carolina State University.
John Ferguson is the product management director for Calibre nmDRC applications at Siemens Digital Industries Software. He has extensive experience in the area of physical verification, including the extension of traditional physical design and verification techniques to such fields as 3DIC and package layout, silicon photonics, quantum computing, and more. John holds several patents and has authored multiple industry publications. He earned a B.Sc. degree in Physics from McGill University, an M.Sc. in Applied Physics from the University of Massachusetts, and a Ph.D. in Electrical Engineering from the Oregon Graduate Institute of Science and Technology (OHSU).
References
1Larry Smith, “Shift left Testing,” Dr. Dobb’s, Sept 1, 2001. https://www.drdobbs.com/shift left-testing/184404768
[ad_2]
Source link
