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During the manufacturing process, chipmakers spanning logic, memory and specialty devices strive to predictably create perfect die at volume with nanoscopic precision. At the same time, they strive to get the most die out of a wafer at the lowest cost. It’s not easy, and our experience suggests that, as chips scale to smaller geometries, it’s only getting harder.
Contending with the rounded or slanted area at the wafer perimeter, commonly referred to as the bevel (Figure 1), has been especially problematic. As layers upon layers are etched to create tiny structures and form next-generation die, the typically smooth bevel surface can become pitted or rough, and films or processing residue can accumulate.
In subsequent steps, these byproducts can often flake off and migrate to active areas of the wafer—potentially causing defects and impacting the ability to yield defect-free uniform die.
History shows that as memory and logic evolve, these challenges compound. Materials used to produce advanced logic and 3D NAND circuitry have generated more byproducts and have greater vulnerabilities; further, wafer-bond packaging techniques place stringent new requirements on bevel flatness and uniformity.
Over the past 15 years, chipmakers have sought to address these bevel-related issues while also maximizing the available area on a wafer from which to create usable chip dies. The advent of immersion lithography techniques in the 2000s elevated the importance of wafer edge integrity because the liquid immersion process is prone to propagation of defect-causing material.
In today’s complex manufacturing environment, increasing die yield is a difficult but critical step to help chipmakers maximize fab productivity and deliver advanced devices cost effectively.
One popular approach in recent years has been bevel etch cleaning, particularly in forming things like shallow trench isolation (STI) structures and contact holes. Lam Research’s bevel etch cleaning has since been used in many strategic points along the fab line, such as post-etch, pre- and post-deposition, and pre-lithography. These measures have proven effective at reducing defect-causing accumulation and boosting device yield up to 0.2-0.5% per step—a significant gain in a high-volume, leading-edge production environment. Additional benefits include greater yield stability and ever-smaller edge exclusion zones.
Bevel etch: Necessary but not enough
While bevel cleaning continues to be necessary, new challenges are emerging as architectures advance. For example, the long wet etch processes used for high aspect ratio 3D NAND trenches require chemistries that often cause severe pitting and damage to the bevel.
Advanced logic devices that use intermediate back-end-of-line (iBEOL) metal interconnects for local routing as part of 3D sequential integration strategies (such as CMOS-over-CMOS) also pose new challenges, because metal lines of copper, tantalum or other materials intrude into the bevel area. Bevel cleaning can be beneficial—but limited—as it can’t protect against unwanted migration of the smallest metal particles.
In addition, broadening adoption of 3D packaging techniques that utilize wafer bonding places very tight restrictions on film variation and profile roll-off at the wafer perimeter, including the bevel, to prevent yield loss in the bonding process. The formation of voids, non-hermeticity, and reduced bonding strength have been identified as issues in the MEMS sector, where wafer bonding is widely used but geometries are less demanding.
The advent of bevel deposition
Fortunately, a new way of addressing these challenges has emerged: selective PECVD deposition of a precisely controlled, tunable dielectric film on the bevel (Figure 2). Among other advantages, this type of deposition process adds a layer of protection prior to demanding processing steps (like extended wet etch), significantly reduces roughness and flatness variation, and reduces contamination and damage risk by encapsulating complex film stacks and their exposed interconnect materials on the bevel.
Another plus is the ability to combine frontside and backside deposition into a single-step process. This is highly desirable for quality, time, and economic reasons, but impossible with many SiO2 deposition or growth processes.
Leading chipmakers have already implemented bevel deposition in advanced fabs around the world. It’s proving to be a game-changer by driving more predictable manufacturing and simplifying 3D integration. Anne Roule, head of the semiconductor platform division at CEA-Leti, recently noted that this “drives significantly higher yield and enables chipmakers to adopt breakthrough production processes” that were previously unfeasible. The use of this bevel-specific technology can cost-effectively boost line and packaging yield significantly across the wafer flow.
Achieving these results in a high-volume environment requires attention to many factors, including protection of the wafer’s active area during bevel deposition. The film stacks used in iBEOL and other types of multilayer interconnect have increasingly tight thermal budgets (another reason traditional thermal oxide processes aren’t suitable for bevel deposition) and are susceptible to damage.
Precise control of the plasma in the bevel area is essential. One effective approach is the use of a toroidal plasma with plasma exclusion zone (PEZ) confinement rings in multiple sizes, which allow accurate shaping of the plasma for optimal results in a highly controlled region, including up to 4 mm of the outer edge of the wafer’s front and back sides.
The ultimate consideration is the deposited film itself, as high degrees of composition flexibility and physical profile tunability are important enablers for engineers who need to tailor solutions for their specific situations. Published research on iBEOL bevel deposition has shown that a SiH4-based, oxide-rich silicon oxynitride film offers a strong combination of purity, wet-etch resistance, bonding edge quality, and protection from metal contamination, and “open[s] the way to process[ing of] complex stacked wafers with various materials in a stringent FEOL environment.”
Results in logic, memory and packaging
Close collaboration with chipmakers and technology partners like CEA-Leti has been critical in Lam’s development of innovative bevel solutions that drive more stability in the manufacturing process. Using these bevel deposition and bevel-etch techniques has enabled semiconductor manufacturers running more than 100,000 wafer starts per month to yield potentially millions of extra die—which could be worth tens of millions of dollars—over the course of a year.
According to Hideshi Miyajima, a technology executive of memory process at Kioxia, the adoption of bevel deposition in Kioxia’s manufacturing process is proving essential to “improving quality in the production process” and in its “ability to provide next-generation flash memory at scale to [Kioxia’s] customers.”
Use of selective PECVD deposition techniques at the wafer perimeter has been shown to significantly boost device and packaging yield for advanced devices currently in production.
Looking ahead, the current results suggest that this added level of wafer bevel control and management may help minimize yield risk during broader introduction of new and highly demanding 3D interconnect and packaging technologies at the 5-nm and 3-nm process generations and beyond.
—Jack Chen is director of engineering at Lam Research.
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